Co-evaluation of FPGA architectures and the CAD system for telecommunication
نویسندگان
چکیده
| We propose an FPGA architecture for next generation B-ISDN telecommunications systems. Such a system requires an FPGA in which an over 10K gates circuit can be implemented and that has a clock cycle rate of 80MHz. While the FPGA architecture has been discussed in terms of its circuit structure, we consider the circuit structure of the FPGA with its CAD tools. We evaluate several FPGA logic-element structures with a technology mapping method. From our experiments, the Multiplexor based logic-element is found to be suitable for implementing such a highspeed circuit using the BDD-based technology mapping method.
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